Prior art computer aided design (CAD) software is known to include complementary tool suites for designing and analyzing the package of a die, e.g., a microprocessor. A “package” is the physical interconnection between the die and, for example, a printed circuit board (PCB). A typical package has several interconnected layers between its top level (Level 1), which connects to the die, and its bottom level (Level 2), which connects to the PCB.
A package “design” is a hierarchical and symbolic digital model of the package circuit. Those skilled in the art appreciate that hardware description languages (HDLs) may be used to formulate this digital model. The digital model consists of linked design elements that simulate the package circuit. The design elements are for example digital representations of the transistors, resistors, logic gates, traces (i.e., intra-level conductors), capacitors, vias (i.e., inter-level connectors), and wire bonds that make up the simulated schematic circuit.
The design elements and interconnections are collated and defined in a design database, which is a textual representation of the package design. The design database may further describe the package design in terms of higher-level cells consisting of two or more design elements, and the connections between cells. Each “net” in the package design describes the linked conductors (e.g., traces of a level and vias between levels) that form a circuit between an input and an output of the package. The CAD software may automatically route traces within a given level of the package design; it may further automatically route vias between levels of the package design.
The design database is processed by the CAD software to perform circuit simulation. The CAD software is for example used to model a signal through the package and over a net (i.e., a “signal net”). Substrate laminate technologies and bond interconnections may also be evaluated through the CAD software.
One exemplary prior art CAD software is Advanced Package Designer (APD) from Cadence Design Systems, Inc., of San Jose, Calif. Such CAD software is known to include verification procedures and dynamic feedback that evaluate design accuracy against a set of physical and electrical design rules, or constraints. Physical design constraints help to ensure manufacturability; electrical design constraints help to ensure electrical specifications of the design. By way of example, this CAD software generates a Design Rule Check (DRC) indicating whether the design meets the various constraints. The prior art CAD software also provides a graphical user interface to view all or part of the package design in two dimensions, for example in a flat or perspective rendition, or with levels overlaid relative to one another.
FIG. 1 illustrates one prior art system 10 for designing a package with prior art CAD software 12. CAD software 12 is stored within a computer 14, initially within a storage unit 16. A processor 18 of computer 14 operates CAD software in response to user inputs at an input interface 20 (e.g., a computer keyboard and mouse). As those skilled in the art appreciate, when initialized, CAD software 12 may also load into internal memory 22 of computer 14. A human designer at input interface 20 then controls CAD software 12, through processor 18, to create a package design 24, also stored within memory 22. The designer can command processor 18 and CAD software 12 to graphically show package design 24 at a graphical user interface 26 (e.g., a computer monitor) of system 10. Illustratively, package design 24 is graphically depicted on a display 28 of graphical user interface 26 as a five-level package model 24A shown in FIG. 2.
FIG. 2 illustrates detail of graphical model 24A. L1 of model 24A couples with a die, and L2 of model 24A couples with a PCB. Levels I(1), I(2) and (3) of model 24A represent intermediate levels of package design 24. Levels L1, I(1), I(2), I(3), L2 are shown as distinct elements and with not-to-scale orientations for ease of illustration. An illustrative signal net 30 is shown from an input connector 32 to an output connector 34 of model 24A. Signal net 30 traverses design elements in the form of traces and vias between connectors 32, 34: via 35 from connector 32 of L1 to trace 36 of I(1); trace 36 within I(1) from via 35 to via 38; via 38 from trace 36 of I(1) to trace 40 of I(2); trace 40 within I(2) from via 38 to via 42; via 42 from trace 40 of I(2) to trace 44 of I(3); trace 44 within I(3) from via 42 to via 46, which terminates at connector 34 of L2. Signal net 30 makes three signal deviations 47 from connector 32 to connector 34; each signal deviation 47 has two via-trace transition points 148 from a via to a trace (e.g., via 35 to trace 36) or from a trace to a via (e.g., trace 40 to via 42).
Another signal net 66 is shown from an input connector 68 to an output connector 70 of model 24A. Signal net 66 traverses design elements in the form of traces and vias between connectors 68, 70: via 72 from connector 68 of L1 to trace 74 of I(2); trace 74 within I(2) from via 72 to via 76, which terminates at connector 70 of L2. Via 72 extends straight through level I(1) without deviating on a trace of level I(1), and is therefore shown as via 72A (between level L1 and I(1)) and via 72B (between level I(1) and I(2)). Similarly, via 76 extends straight through level I(3) without deviating on a trace of level I(3), and is therefore shown as via 76A (between level I(2) and I(3)) and via 76B (between level I(3) and L2). Signal net 66 makes one signal deviation 77 from connector 68 to connector 70; signal deviation 77 has two via-trace transition points 178 from a via to a trace (e.g., via 72 to trace 74) or from a trace to a via (e.g., trace 74 to via 76).
With further regard to FIG. 1, CAD software 12 is also operable to generate a design database 50. In one example, design database 50 textually defines signal nets 30 and 66 of FIG. 2: signal net 30 is defined by connectors 32, 24, traces 36, 40, 44, and vias 35, 38, 42, 46; signal net 66 is defined by connectors 68, 70, trace 74, and vias 72A, 72B, 76A, 76B. Design database 50 also includes parameters (often called a “netlist”) to ensure that signal nets 30 and 66 have start and end points (i.e., connectors 32, 34 for signal net 30, and connectors 68, 70 for signal net 66). A designer can manipulate design database 50 to develop the desired package design 24.
CAD software 12 utilizes design rules 52 to generate one or more DRCs 54 in the event that a design element or signal net of package design 24 exceeds a manufacturing constraint or electrical specification. By way of example, design rules 52 may specify that a trace width of trace 36 is 20 μm, to ensure manufacturability. If a designer of system 10 implements trace 36 with 10 μm, for example, then CAD software 12 generates a DRC 54A, which may be graphically displayed on model 24A, as shown in FIG. 2. The user is thus made aware that a problem may exist with trace 36.
Those skilled in the art appreciate that package design 24 often has more than the five levels illustrated in model 24A; however only five levels are shown in FIG. 2 for ease of illustration. For example, it is common that package design 24 include ground levels between each level with signal traces (I(1), I(2) and I(3); however these ground levels are not shown to simplify illustration. Those skilled in the art also appreciate that package design 24 also typically has many more signal nets and other design elements than illustrated signal nets 30 and 66. For example, package design 24 typically includes many other traces and vias (not shown) within package model 24A.
FIG. 3 illustrates package model 24A in a side view. FIG. 3 further illustrates how package design 24 connects between a die 80 and a PCB 82. Connector 32 is for example a pad that connects with a solder ball 84 of die 80; connector 34 is for example a pad that connects with signal wires of PCB 82. Similarly, connector 68 is for example a pad that connects with a solder ball 86 of die 80; connector 70 is for example a pad that connects with signal wires of PCB 82. FIG. 3 also clearly shows that signal net 30 has more signal deviations 47 than the single signal deviation 77 of signal net 66.
The increased complexity of the modem die has correspondingly increased the complexity of the package design. An example of a complex die includes a Precision Architecture—Reduced Instruction Set Computer (PA-RISC) processor produced by Hewlett Packard Corporation, which has over one billion components. The package for the PA-RISC processor must maintain high signal integrity through its signal nets; however the prior art CAD software does not simulate this signal integrity as required by the corresponding die. Accordingly, the package may be physically manufactured, at great expense, before the designer learns that the package is not suitable for operation with the die. Moreover, while the DRCs generated by the prior art CAD software may assist in manufacturability; they do not, however, warn the designer of signal net incompatibilities between the die and the package. By way of example, prior art CAD software 12 does not evaluate signal deviations 47, 77 of package model 24A. Each signal deviation 47, 77 may however cause signal distortions and delays that seriously impact signal integrity from die 80 to PCB 82. In addition, if signal nets 30, 66 operate on a common clock, the respective signals of signal nets 30, 66 from die 80 through package design 24 may be distinctly different at PCB 82, due to deviations 47, 77, thus creating undesirable non-synchronization between the signals at the PCB.